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LSI/CSI
UL
(R)
LS7031
(631) 271-0400 FAX (631) 271-0405 December 2002
CONNECTION DIAGRAM - TOP VIEW SCAN RESET INPUT MSD STROBE 8 ST R O BE 7 ST R O BE 6 ST R O BE 5 DIGIT STROBE OUTPUTS ST R O BE 4 ST R O BE 3 ST R O BE 2 LSD STROBE 1 DECIMAL POINT INPUT BLANK OUTPUT 1 2 3 4 5 6 7 8 9 10 11 LS7031 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 OSC. INPUT SCAN INPUT N.C. B1/D1 B2/D1 N.C. B4/D1 B8/D1 N.C. B1/D2 B2/D2 B4/D2 B8/D2 V SS V GG N.C. N.C. V DD RESET COUNTER INPUT LOAD LATCH INPUT INPUT TO DECADE 2 LATCH INPUT TO DECADE 1 LATCH LSI
LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747
A3800
6 DECADE MOS UP COUNTER WITH 8 DECADE LATCH AND MULTIPLEXER
FEATURES: * DC to 7.5 MHz Count Frequency * Multiplexed BCD Outputs * DC to 500kHz Scan Frequency * +4.75V to +15V Operation (VDD-VSS) * Compatible with CMOS Logic * High Input Noise Immunity * Ability to Latch External BCD Data in the two LSD Positions * Leading Zero Blanking with Decimal Point and Overflow Controls * All inputs protected * Low Power Dissipation * 40 Pin DIP - See Figure 1 DESCRIPTION: The LS7031 is a monolithic, ion implanted MOS, 6 decade up counter. The circuit includes latches, a multiplexer, leading zero blanking and BCD data outputs. CLOCK GENERATOR The clock for the six decade counter (digit positions 3-8) is formed from the internal `OR' combination of B4/D2 and B8/D2 if LS7031 is used with external prescaling counters. When operated in this fashion the maximum allowable propagaton delay between B4/D2 (H-L) and B8/D2 (L-H), measured at Vss - 1V, is 10ns. If used as a straight six decade counter, clock pulses may be applied to inputs B4/D2 or B8/D2 with the unused input held low. In either mode of operation total pulse width must be minimum 62ns. See Block Diagram. 6 DECADE UP COUNTER The six decade ripple through counter increments on the negative edge of the input count pulse. Maximum ripple time is 12s (999999 to 000000). Maximum count frequency is 7.5MHz.
OVERFLOW OUTPUT 12 OVERFLOW INPUT 13 DECADE 8 OUTPUT, DECADE 7 OUTPUT, DECADE 6 OUTPUT, D8 D7 D6 B8 BCD DATA OUTPUTS B4 B2 B1 14 15 16 17 18 19 20
FIGURE 1
DIGIT STROBES Timing of Digit Strobes is arranged such that both edges of strobe are guardbanded by a minimum 400ns within valid BCD data when scan frequency is 100kHz or less. The guardband is a minimum of RESET 200ns at 250kHz scan frequency. At 500kHz only negative edge of All 6 counter decades are reset to zero when Reset input is brought Strobe is guaranteed to be within valid BCD data by a minimum low for a minimum of 4s. The Overflow flip-flop is reset at the 200ns. same time. Reset must be high for a minimum of 1s before next valid count can be recorded. OVERFLOW The Overflow flip-flop sets on the first negative transition of the OverSCAN OSCILLATOR AND COUNTER flow Input and remains set until Reset is brought low. Data is transThe scan counter is driven by an internal oscillator whose ferred from Overflow flip-flop to Overflow Latch when Load is brought frequency is determined by a capacitor connected between low. A high at the Overflow Latch causes display to unblank. OverOscillator input and Scan input. An external scan clock applied flow Output is output of Overflow Latch. MSB outputs of Decades to Scan input can also drive the scan counter. Scan counter 6, 7, 8 are available for use as Overflow Input. advances on negative edge of scan clock. The counter scans from MSD to LSD. When Scan Reset input is LATCHES brought high the scan counter is forced to MSD state. Internal Eight decades of latch are provided, two for storage of the two synchonization guarantees proper scanning no matter when Scan external least significant decade counters and the remaining 6 for inReset is brought low relative to scan clock. Maximum scan ternal counter outputs. All latches when Load signal is brought low frequency is 500kHz. for a minimum of 4s and kept low until a minimum of 12s has elapsed from previous negative edge of count pulse (ripple time). DECIMAL POINT Storage of valid data occurs when Load signal is high for a minimum A high at the Decimal Point input resets the Blanking flip-flop of 1s before next negative edge of count pulse or reset. Data is causing the display to unblank. Decimal Point should be brought transferred from Overflow flip-flop to Overflow latch at the same time. high at start of digit time which has active Decimal Point.
7031-121102-1
BLANKING Leading zero blanking is employed. At start of each MSD to LSD scan, display is blanked until a non-zero digit or active decimal point is encountered. Display unblanks during LSD time and whenever Overflow output is high. When Scan Reset is applied, display blanks to prevent display damage. Blanking information is available at Blank output. BCD DATA Data is available in multiplexed BCD format. BCD data can be readily demultiplexed using Digit Strobes as latch enable signals. MAXIMUM RATINGS PARAMETER Storage Temperature Operating Temperature Voltage (any pin to Vss) SYMBOL Tstg TA Vmax VALUE -65 to +150 -25 to +70 -30 to +0.5
POWER SUPPLIES +4.75V to +15V single power supply operation is obtained when VGG and VDD are tied together. Inputs and outputs are CMOS compatible and Minimum Input Noise Immunity of 25% of power supply is guaranteed except for Decade 1 and 2 inputs. (All inputs are TTL compatible at +4.75V to +5.25V operation.) With VGG at -12V, VDD at OV and Vss at +5V all inputs are TTL and CMOS compatible. All outputs are CMOS compatible and BCD and BLANK outputs also provide standard TTL compatibility. In addition, Overflow Output is low power TTL compatible. In either mode outputs swing between VDD and Vss.
UNITS C C V
DC ELECTRICAL CHARACTERISTICS (VDD = VGG= OV, Vss = +4.75 to +15V, -25C TA +70C unless otherwise specified.) PARAMETER SYMBOL MIN Operating Supply Current Idds (fC = 7.5MHz) Input Noise Immunity Low and High Vni 25% (Vss-VDD) EXTERNAL Input Voltage "0" Vil Vss - 20 DECADE Input Voltage "1" Vih Vss - 1.0 INPUTS
MAX 15
UNITS mA
Vss - 3.95 Vss +0.2 -
V V V V V
{
D6, D7, D8 OF, BCD Blank (See Note 1)
{
Output Voltage "0" Output Voltage "1" Output Voltage "0" (sinking 10A) Output Current "1"
Vol Voh
Vss - 1.0
Vol
-
+0.5
V
Segment and Strobe Outputs (See Note 2)
Vss = 4.75V(Voh = Vss - 0.5V) (Voh = Vss - 1V) (Voh = Vss - 4V) Vss = 10V (Voh = Vss - 2V) (Voh = Vss - 3V) Vss = 15V (Voh = Vss - 2V) (Voh = Vss - 3V)
-
0.05 0.25 0.90 2.0 3.0 3.0 4.5
-
mA mA mA mA mA mA mA
NOTE 1: Current Sink = Same as segment and strobe outputs. Current Source = N/A at Voh = Vss - 0.5V for Vss = +4.75V 35A at Voh = Vss -1V for Vss = +4.75V 40% of segment and strobe outputs at all other specified operating points. NOTE 2: Limit segment current to 6mA maximum. The following inputs have internal pull down resistors to VDD with maximum sink current of 5A at Vss input. Scan Reset B1/D1 B1/D2 Decimal B2/D1 B2/D2 Overflow B4/D1 B4/D2 B8/D1 B8/D2 TTL COMPATIBLE OUTPUTS: POWER SUPPLIES: Vss = +5V 5%, VDD = 0V, VGG = -12V 5% OUTPUT LEVELS: "1" Level Vss - 0.5V (sourcing 100A) "0" Level 0.4V (sinking 1.6mA) "1" Level Vss -.5V (sourcing 40A) "0" Level 0.4V (sinking .18mA) SCAN OSCILLATOR CAPACITANCE TYPICAL OSCILLATOR FREQUENCY 4.75V 40.0 kHz 22.2 kHz 5.0 kHz 10V 24.2kHz 14.8kHz 3.6kHz 15V 22.2 kHz 13.8 kHz 3.5 kHz
} }
BLANK AND BCD DATA OUTPUTS OVERFLOW OUTPUT
50pF 100pF 470pF
All other outputs as specified for single power supply, Vss = +15V operation. Inputs as specified for single power supply, Vss = +5V 5% operation.
7031-110201-2
ELECTRICAL CHARACtERISTICS: (VDD = VGG = OV, Vss = +4.75 to +15V, -25C TA +70C unless otherwise specified.) PARAMETER Count Test and Count frequency (Vss = +5V 5%) (Vss = +10V) (Vss = +15V) Scan frequency SYMBOL fc, ftc fc, ftc fc, ftc fsc MIN DC DC DC DC MAX 7.5 6 5 500 UNITS MHz MHz MHz kHz
Count Pulse Width (Pulse applied to B4/D2 or B8/D2; `OR' combination ofB4/D2 and B8/D2) (Vss = +5V 5%) (Vss = +10V) (Vss = +15V) **Propagation Delay (B4/D2(H-L) to B8/D2 (L-H) at Vss -1.0V) Count Ripple Time Load Pulse Width Load Removal Time Reset Pulse Width Reset Removal Time Rise and Fall Time Count Pulse Reset Pulse Test Count Pulse *Strobe Guard Band time (fSC 100kHz 250kHz) *Strobe Guard Band time (100kHz fSC 250kHz) *Strobe Guard Band time (250kHz fSC 500kHz) negative edge only tcpw tcpw tcpw 62 83 100 ns ns ns
tcr tlpw tlr trpw trr
Overlap 4 4 -
10 1 1
ns s s s s
trfc trfr trftc tgb tgb tgb
400 200 200
4 4 80 -
s s s ns ns ns
The information included herein is believed to be accurate and reliable. However, LSI Computer Systems, Inc. assumes no responsibilities for inaccuracies, nor for any infringements of patent rights of others which may result from its use.
*Defines the minimum time from strobe edges to switching BCD data.
BCD
750MHz
PRESCALE DIGIT 1 BCD CNTR 1
75MHz
PRESCALE DIGIT 2 BCD CNTR 2
tgb
tgb
1 2 4 8 1 2 4 8
7.5MHz
STROBE
B1/D1 - B8/D1
FIGURE 2. GUARD BANDED STROBE
B1/D1 - B8/D1 LS7031
DIGIT STROBES
**Propagation Delay and Pulse Width Vss - 1.0 B4/D2
(MSD) (LSD)
1
2
4
8
BLANK
DIGIT DRIVERS
BCD TO SEVEN SEGMENT DECODER/DRIVER
tpr
B8/D2
Vss - 1.0
abcdefg
tcpw
B4/D2 or B8/D2
8 DIGIT DISPLAY
FIGURE 3. TYPICAL APPLICATION
7031-110201-3
DECIMAL POINT INPUT 10 SCAN RESET INPUT (RESET TO MSD) 1 LSD MSD OUTPUT BUFFERS 8 DIGIT STROBE OUTPUTS 9 8 7 6 5 4 3 2
27 Vss 26 VGG BLANKING F/F S R Q 11 BLANK OUT 23 VDD
OSC. INPUT
NZ 40 OSCILLATOR OR BUFFER R C LSD 8 STATE STATIC SCAN COUNTER & DECODED MSD
SCAN INPUT
39 8 1 2 3 4 B1 B2 B4 B8 B1 B2 B4 B8 12 48 G MUX GATE 12 48 G MUX GATE 12 48 G MUX GATE 5 B1 B2 B4 B8 12 48 G MUX GATE 12 48 G MUX GATE 6 B1 B2 B4 B8 12 48 G MUX GATE 12 48 G MUX GATE B1 B2 B4 B8 B8 12 48 G MUX GATE 17 DATA OUTPUT BUFFER B1 B2 B4 20 19 BCD DATA OUTPUT 18 7
OVERFLOW 12 OUTPUT 4 BIT LATCH ST LOAD LATCH 21 INPUT 1248 BCD C COUNTER R 37 36 34 33 B1 B2 B4 B8 DIGIT ONE 31 30 29 28 B1 B2 B4 B8 DIGIT TWO 16 15 D7 OUTPUT 14 D8 OUTPUT 1248 C BCD COUNTER R 1248 BCD C COUNTER R 1248 C BCD COUNTER R 12 48 C BCD COUNTER R 1248 C BCD COUNTER R 4 BIT LATCH ST 4 BIT LATCH ST 4 BIT LATCH ST 4 BIT LATCH ST 4 BIT LATCH ST 4 BIT LATCH ST 4 BIT LATCH ST 1 BIT LATCH
ST
13 OVERFLOW INPUT C R OVFLW F/F
RESET INPUT 22
FIGURE 4. LS7031 BLOCK DIAGRAM
D6 OUTPUT

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